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    dc.contributor.authorRiaño Bejar, Erika Viviana.-
    dc.date.accessioned2022-12-15T21:59:15Z-
    dc.date.available2018-
    dc.date.available2022-12-15T21:59:15Z-
    dc.date.issued2018-
    dc.identifier.citationRiaño, E. V. (2017). Caracterización de problemas a solucionar mediante programación multiproceso de memoria compartida [Trabajo de grado pregrado, Universidad de Pamplona]. Repositorio Hulago Universidad de Pamplona. http://repositoriodspace.unipamplona.edu.co/jspui/handle/20.500.12744/5479es_CO
    dc.identifier.urihttp://repositoriodspace.unipamplona.edu.co/jspui/handle/20.500.12744/5479-
    dc.descriptionEl autor no proporciona la información sobre este ítem.es_CO
    dc.description.abstractEl autor no proporciona la información sobre este ítem.es_CO
    dc.format.extent315es_CO
    dc.format.mimetypeapplication/pdfes_CO
    dc.language.isoeses_CO
    dc.publisherUniversidad de Pamplona – Facultad de Ingenierías y Arquitectura.es_CO
    dc.subjectEl autor no proporciona la información sobre este ítem.es_CO
    dc.titleCaracterización de problemas a solucionar mediante programación multiproceso de memoria compartida.es_CO
    dc.typehttp://purl.org/coar/resource_type/c_7a1fes_CO
    dc.date.accepted2017-
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    dc.relation.referencesSima, D., Fountain, T. J., Kacsuk, P., Sima, D., Fountain, T. J., & Kacsuk, P. (n.d.). Part IV . Chapter 15 - Introduction to MIMD Architectures Thread and process-level parallel architectures are typically realised by MIMD ( Multiple Instruction Multiple Data ) computers . This class of parallel computers is the most general one since it permits autonomous operations on a set of data by a set of processors without any architectural restrictions . Instruction level data-parallel architectures should satisfy several constraints in order to build massively parallel systems . For example processors in array processors , systolic architectures and cellular automata should work synchronously controlled by a common clock . Generally the processors are very simple in these systems and in many cases they realise only a special function ( systolic arrays , neural networks , associative processors , etc .). Although in recent SIMD architectures the complexity and generality of the applied processors have been increased , these modifications have resulted in the introduction of process-level parallelism and MIMD features into the last generation of data-parallel computers ( for example CM-5 ), too . MIMD architectures became popular when progress in integrated circuit technology made it possible to produce microprocessors which were relatively easy and economical to connect into a multiple processor system . In the early eighties small systems , incorporating only tens of processors were typical . The appearance of Transputer in the mid-eighties caused a great breakthrough in the spread of MIMD parallel computers and even more resulted in the general acceptance of parallel processing as the technology of future computers . By the end of the eighties mid-scale MIMD computers containing several hundreds of processors become generally available . The current generation of MIMD computers aim at the range of massively parallel systems containing over 1000 processors . These systems are often called scalable parallel computers . 15 . 1 Architectural concepts The MIMD architecture class represents a natural generalisation of the uniprocessor von Neumann machine which in its simplest form consists of a single processor connected to a single memory module . If the goal is to extend this architecture to contain multiple processors and memory modules basically two alternative choices are available : a . The first possible approach is to replicate the processor / memory pairs and to connect them via an interconnection network . The processor / memory pair is ca…, 1–es_CO
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